1. Field of the Invention
The present invention relates to non-volatile digital memories, and more particularly, to improved-FLASH EPROM memory technology.
2. Description of Related Art
FLASH EPROMs are a growing class of non-volatile storage integrated circuits. These FLASH EPROMs have the capability of electrically erasing, programming or reading a memory cell in the chip. The memory cells in a FLASH EPROM are formed using so-called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide or other insulating material, and insulated from the control gate or wordline of the transistor by a second layer of insulating material.
The act of charging the floating gate is termed the "program" step for a FLASH EPROM. This is accomplished through so-called hot electron injection by establishing a large positive voltage between the gate and source, as much as twelve volts, and a positive voltage between the drain and source, for instance, seven volts.
The act of discharging the floating gate is called the "erase" function for a FLASH EPROM. This erase function is typically carried out by a F-N tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase). For instance, a source erase operation is induced by establishing a large positive voltage from the source to gate, while floating the drain of the respective memory cell. This positive voltage can be as much as twelve volts.
Details concerning the structure and function of prior art FLASH EPROMS can be seen upon review of the following U.S. Patents which are incorporated by reference for the purpose of teaching the background of related technology:
Mukherjee, et al., U.S. Pat. No. 4,698,787 issued Oct. 6, 1987; PA1 Holier, et al., U.S. Pat. No. 4,780,423 issued Oct. 25, 1988. PA1 defining a plurality of drain diffusion regions elongated in a first direction; PA1 doping the drain diffusion regions; PA1 establishing a tunnel insulating material on the substrate at least in regions adjacent the drain diffusion regions; PA1 establishing a floating gate conductive material over the tunnel insulating material at least in regions adjacent the drain diffusion-regions; PA1 establishing a control gate insulating material over the floating gate conductive material; PA1 exposing elongated source diffusion regions through the floating gate conductive material in the substrate, and aligned with the floating gate conductive material; PA1 doping the source diffusion regions; PA1 establishing an insulating layer over the source diffusion regions and any exposed floating gate conductive material; and PA1 forming a plurality of rows of conductive material over the control insulating material and floating gate conductive material. PA1 establishing tunnel insulating material over the substrate at least in elongated channel regions; PA1 establishing a floating gate conductive material over the tunnel insulating material at least in the elongated channel regions; PA1 establishing a control gate insulating material over the floating gate conductive material; PA1 exposing elongated source diffusion regions and drain diffusion regions in the substrate, aligned with the floating gate conductive material; PA1 doping the drain diffusion regions with a first distribution of dopants; PA1 doping the source diffusion region with a second distribution of dopants; PA1 growing an insulating layer over the source and drain diffusion regions and any exposed floating gate conductive material; and PA1 forming a plurality of rows of conductive material over the control insulating material and floating gate conductive material:
More advanced technology concerning FLASH EPROM integrated circuits on set out in Woo, et al., "A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology" IEDM 1990, Published by the IEEE, pages 91-94. Also, Woo, et al., "A Poly-Buffered "FACE" Technology for High Density Memories", 1991 SYMPOSIUM ON VLSI TECHNOLOGY, pages 73-74. One prior art "contactless" array EPROM architecture is described in Kazerounian, et al., "Alternate-Metal Virtual Ground EPROM Array Implemented In A 0.8 .mu.M Process for Very High Density Applications", IEDM, published by IEEE, 1991, pages 11.5.1-11.5.4.
As evidenced by the Woo, et al. and Kazerounian, et al. publications, there is increasing interest in contactless array non-volatile memory design. So-called contactless arrays include an array of storage cells which are coupled to one another by buried diffusion, and the buried diffusion is only periodically coupled through contacts to a metal bitline. Earlier FLASH EPROM designs such as the Mukherjee, et al. system required a "half" metal contact for each memory cell. Because metal contacts use a significant area on an integrated circuit they are a major impediment to creating a high density memory technology. Furthermore, as the device becomes smaller and smaller, the area reduction becomes limited by the metal over contact pitches of adjacent drain and source bitlines used to access the storage cells in the array.
Therefore, it is desirable to provide a FLASH EPROM cell, EPROM architecture, and a method of fabricating the same which results in a high density non-volatile memory circuit.